The Intel Pentium microprocessor was introduced on March 22, 1993. Its microarchitecture, dubbed P5, was Intel's fifth-generation and first superscalar IA-32 microarchitecture. As a direct extension of the 80486 architecture, it included dual integer pipelines, a faster floating-point unit, wider data bus, separate code and data caches and features for further reduced address calculation latency.
The P5 Pentium competitors included the Motorola 68060 and the PowerPC 601 as well as the SPARC, MIPS, and Alpha microprocessor families, most of which also used a superscalar in-order dual instruction pipeline configuration at some time.
The early versions of 60-100 MHz P5 Pentiums had a problem in the floating point unit that resulted in incorrect (but predictable) results from some division operations. This bug, discovered in 1994 by professor Thomas Nicely at Lynchburg College, Virginia, became known as the Pentium FDIV bug and caused embarrassment for Intel, which created an exchange program to replace the faulty processors.
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The first Pentium microprocessor core was code-named "P5". Its product code was 80501. There were two versions, specified to operate at 60 MHz and 66 MHz respectively. This first implementation of the Pentium used a traditional 5 Volt power supply (descended from the usual TTL logic compatibility requirements). It contained 3.1 million transistors and measured 16.7 mm by 17.6 mm for an area of 293.92 mm^2. It was fabricated in a 0.8 µm BiCMOS process. The 5 volt design resulted in relatively high energy consumption for its operating frequency compared to the later models.
They also had (for the time) high heat production due to their 5 V operation, and were often known colloquially as "coffee warmers" or some similar nickname.
A80501-60 Specification Details |
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The P5 was followed by the P54C (80502); there were versions specified to operate at 75, 90, or 100 MHz using a 3.3 volt power supply. This was the first Pentium processor to operate at a 3.3 volts, reducing energy consumption. It employed an internal clock multiplier to let the internal circuitry work at a higher frequency than the external address and data buses, as it is more complicated and cumbersome to increase the external frequency, due to physical constraints. It contained 3.3 million transistors and measured 163 mm^2. It was fabricated in a BiCMOS process which has been described as both 0.5 µm and 0.6 µm due to differing definitions.
Continue reading: (see P54CS, below)
A80502-75 Specification Details |
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BP80502-75 Specification Details |
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A80502-90 Specification Details |
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A80502-100 Specification Details |
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BP80502-100 Specification Details |
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A80502120 Specification Details |
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The P54CQS was followed by the P54CS, which operated at 133, 150, 166 and 200 MHz. It contained 3.3 million transistors, measured 90 mm^2 and was fabricated in a 0.35 µm BiCMOS process with four levels of interconnect.
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A80502150 Specification Details |
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A80502166 Specification Details |
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FV80502166 Specification Details |
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FV80502200 Specification Details |
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A80502120 Specification Details |
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